(n-well) CMOS Process = nFETs and pFETs are available all p-n junction must be reversed bias
We create a silicon-oxide “stencil” (or mask) We get highly repeatable gates because the gate acts as a stencil as well N-type ND P-type NA First-Principles Modelĥ A MOSFET Transistor Source Drain Gate Drain Gate Source SubstrateĦ Self-Aligned Process How do we make a basic transistor element?
Ec qDV Ec E0 Ec Ef Case I: P(E) ~ exp( - E0 /kT) Case II: P(E) ~ exp( - ( E0 - qDV)/kT) Ratio of Case II to Case I = 1 P(E) = ~ e-(E-Ef)/kT 1 + e-(E-Ef)/kT exp( DV / UT ) UT = kT/qģ P-N Junctions Depletion Layer or Region N-type ND P-type NA qND Charge
0 kommentar(er)
